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Use of the RISC-V instruction set only in a Open-source FPGA design (license question)

I have started to create a VHDL design for new architecture. Now I'm thinking about the used instruction set. Could create an own encoding of the used machine code, but must create a C compiler for it or port the architecture to an existing compiler like GCC. Also must write an assembler, if I use an own instruction set.


What are the license requirements for me as developer, when I want use any specific parts of the RISC-V instruction set only? Would also to add some specific processor control registers and a modified base architecture. Might be security by obscurity, but control registers where I can setup the end of the stack and the size in privileged mode. Also two types of the stack. Return address and data, both separately as example.


BTW: The project is currently for the purpose of education only. Without interest from me to sell this maybe exotic (not RISC-V itself, but my modifications) architecture.




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Use of the RISC-V instruction set only in a Open-source FPGA design (license question)

I have started to create a VHDL design for new architecture. Now I'm thinking about the used instruction set. Could create an own encoding of the used machine code, but must create a C compiler for it or port the architecture to an existing compiler like GCC. Also must write an assembler, if I use an own instruction set.


What are the license requirements for me as developer, when I want use any specific parts of the RISC-V instruction set only? Would also to add some specific processor control registers and a modified base architecture. Might be security by obscurity, but control registers where I can setup the end of the stack and the size in privileged mode. Also two types of the stack. Return address and data, both separately as example.


BTW: The project is currently for the purpose of education only. Without interest from me to sell this maybe exotic (not RISC-V itself, but my modifications) architecture.




https://redd.it/1kkd6me
@r_riscv

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